Semiconductor package



FIG. 1 is a perspective view of a semiconductor package showing our new design;

FIG. 2 is a top plan view thereof;

FIG. 3 is a left side elevational view thereof;

FIG. 4 is a front elevational view thereof;

FIG. 5 is a bottom plan view thereof;

FIG. 6 is a right side elevational view thereof;

FIG. 7 is a rear elevational view thereof;

FIG. 8 is a perspective view of another embodiment of a semiconductor package showing our new design; and,

FIG. 9 is a front elevational view of the embodiment of FIG. 8.

The rest of veiws of the embodiment of FIG. 8 are the same as those of the embodiment of FIG. 1. 

The ornamental design for a semiconductor package, as shown and described 